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I know the 32 bit registers were named like the 16 bit registers with an 'E' prefix to mean extended. I've always assumed that meant extended from 16 to 32 bits although I've never seen that explicitly stated.

I was trying to find out what the 'R' stands for but my google skills have failed me. Anyone know?

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up vote 9 down vote accepted

It means register, and it isn't all for historical reasons.

The historical part is that Intel got itself into the habit of enumerating registers with letters with the 8008 (A through E plus H and L). That scheme was more than adequate at the time because microprocessors had very few registers and weren't likely to get more, and most designs did it. The prevailing sentiment then was that software would be rewritten for new CPUs as they appeared, so changing the register naming scheme between models wouldn't have been a big deal. Nobody foresaw the 8088 evolving into a "family" after being incorporated into the IBM PC, and the yoke of backward compatibility pretty much forced Intel into having to adopt schemes like the "E" on 32-bit registers to maintain it.

The non-historical part is all practical. Using letters for general-purpose registers limits you to 26, fewer if you weed out those that might cause confusion with the names of special-purpose registers like the program counter, flags or the stack pointer.

I don't have a source to confirm it, but I suspect the choice of R as a prefix and the introduction of R8 through R15 on 64-bit CPUs signals a transition to numbered registers, which have been the norm among 32-bit-and-larger architectures not derived from the 8008 for almost half a century. IBM did it in the 1960s with the 360 and has been followed by the PowerPC, DEC Alpha, MIPS, SPARC, ARM, Intel's i860 and i960 and a bunch of others that are long-forgotten.

You'll note that the existing registers would fit nicely into R0 through R7 if they existed, and it wouldn't surprise me a bit if they're treated that way internally. The existing long registers (RAX/EAX/AX/AL, RBX/EBX/BX/BL, etc.) will probably stay around until the sun burns out.

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A bit anticlimactic but I guess I shouldn't be too surprised. Thanks. –  Matt Jan 1 '12 at 5:28
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That was all the drama I could muster. :-) –  Blrfl Jan 1 '12 at 15:06
    
+1 for the very interesting read. But if it was to be summarized in just one line, it would have been the answer that I gave. All this rich and interesting information gets folded down to "historical reasons" if summarized. –  Mike Nakis Jan 5 '12 at 19:48
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It just means 'register'. For historical reasons.

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In the earlier processors, not all registers were equal:

  • There was not enough space on the chips to have an adder unit for each register.
  • With 8 bits, there weren't enough opcodes available for all possible combinations of source and destination.

So assuming that one specific register was always implicated when the adder was involved, made the chip less complex and opcodes shorter.

E.g. the 6510 (used in Commodore 64) could only add using register A, and indexing used either X or Y. There are INC X and INC Y instructions, but no INC A.

As registers had different usages, mnemonics were chosen reflecting their usage. E.g. the A, X, and Y in the 6510 (instead of A, B, and C).

The names in the 8086 are chosen to reflect their usage as well. With 4 general purpose registers, it was logical to name them AX, BX, CX, and DX. Additional indexing registers were called BP and SP (mnemonic: Base Pointer, Stack Pointer).

As many opcodes were extended to 16 bits, there was some space to indicate which one out of four register was used. However, some of the historical reasons still applied, as CX was a bit special: REP and the likes, which are 8 bit opcodes, always use CX as the counter. A simple mnemonic, CX = Counter, helps to remember which one is used.

The opcodes for successors to the 8086 had to be backwards compatible, and are a mess as a result of the variable length opcodes. When 32 bit busses became more common, processors with fixed opcode length were tried. This simplifies the decoding part of the CPU, which freed up space that could be used for e.g. more registers.

Processors that followed this line of thought are called RISC processors (Reduced Instruction Set CPU), to contrast with the CISC (Complex Instruction Set CPU).

More registers results in less spill-over to memory. Basically, registers are the fastest cache available, so increasing the number of registers is a good idea, even nowadays. The lack of specialized instructions was (hopefully more than) compensated by the faster through-put of simple instructions.

Fixed length 32 bit opcodes have enough space to include a source, a second source, an operation, and a destination. SPARC managed to wringle 5 bits for each of the source, second source, and destination, and therefor had 32 registers visible at the same time.

32 registers are too many to use letters, and they were mostly equal anyway, so numbering them was the obvious choice. The 'R' was used to distinguish them from the constants 0..31, and 'R' was an easy mnemonic for Register. Therefore: R0..R31.

Over the years, the Pentium and its successors have maintained backwards compatiblity. However, many of the more succesfull RISC ideas were incorperated as well. Frequently, those new, RISC-like instructions will run faster than the backwards compatible versions.

The number of registers was also increased by Intel, to reduce the number of memory accesses.

And apparently, Intel finally has started to use the R-notation. Backwards compatibility will ensure that AX, BX, ... will stay, but I would bet that AX is just a synonym for e.g. R0.


Disclaimer: The above is my view on history. It will be incomplete as I wasn't around to witness the earlier parts of history first hand. Nevertheless, I hope it is useful to some.

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The 6500 family really had no need for a dedicated instruction to increment the accumulator because an immediate-mode add of 1 took the same two cycles as an INX or INY, although the code occupied an additional byte. I wrote a lot of assembly for that chip and in practice that kind of increment was rare outside of doing math that needed it. –  Blrfl Dec 31 '11 at 22:28
    
@Blrfl You are right: ADD 1 works so there was no need for a specialized 'Increase A'. And I don't recall needing it either. –  Sjoerd Jan 1 '12 at 4:31
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