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This is what I guess would happen:

  1. If two cores tried to access the same address in RAM, one would have to wait for the other to access the RAM. The second time that each core would try to access the same address, they may still have that RAM cached, so they could access their respective caches simultaneously.

  2. If two cores tried to access different addresses in the same RAM, one would have to wait for the other to access the RAM.

In other words, I would imagine that for RAM intensive programming tasks, multiprocessing won't help much unless it involved reading from the same address in RAM multiple times per core.

So, can multiple CPU's / cores access the same RAM simutaneously, or is what I'm saying correct?

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I can't speak to the hardware level you're referring to, but I can say ram intensive tasks can be aided by multiprocessing by simply splitting up the usage; that is to say if you have 500mb of data in ram you need processed, give out 250mb of that data/ram to one proc and 250mb to another and you've effectively doubled your possible throughput (ram bandwidth restrictions not withstanding). Aside from whether or not the hardware can do it, having multiple processors accessing the same ram address is a genuinely bad idea, and most multi-proc code painstakingly tries to avoid it. –  Jimmy Hoffa Jan 15 '13 at 15:35
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@JimmyHoffa But RAM bandwidth restrictions are precisely what he's talking about (as the assumption is that the task is memory-bound). –  delnan Jan 15 '13 at 15:36
    
@Jimmy I don't see any problem with two processors trying to read from the same RAM address. I would only see a problem if they tried to write to it at the same time. –  Lost Hobbit Jan 15 '13 at 15:43
    
@delnan Ah, I didn't get that at all from the question. I don't see how concurrent ram address access however has any effect on ram bandwidth. Say for instance you give 1-200 to one proc and 201-400 to another proc, if you fill both ranges with identical data then concurrent address access is subverted. Whether or not there is concurrent ram access at all disregarding addresses is however a question. I would presume yes but I know near nothing about hardware behaviour at this level. –  Jimmy Hoffa Jan 15 '13 at 15:44
    
@JimmyHoffa Note that these days the memory controller is built into the CPU die itself and is shared between physical cores. Depending on the access pattern and RAM bandwidth it could be a case that a single thread is bandwidth bound. In that case adding another thread working on memory intensive tasks won't help because there's a physical limitation. It would help if there was another physical processor present in the machine with it's own memory controller, but even still the bandwidth of the link(AMD's HT and Intel's QPI) between CPU and RAM could become a bottleneck. –  zxcdw Jan 15 '13 at 15:57
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2 Answers

up vote 4 down vote accepted

Summary: it's generally possible for a single core to saturate the memory bus if memory access is all it does.

If you establish the memory bandwidth of your machine, you should be able to see if a single-threaded process can really achieve this and, if not, how the effective bandwidth use scales with the number of processors.


The details will depend on the architecture you're using. Assuming something like modern SMP and SDRAM:

  1. If two cores tried to access the same address in RAM ...

    could go several ways:

    • they both want to read, simultaneously:

      • two cores on the same chip will probably share an intermediate cache at some level (2 or 3), so the read will only be done once. On a modern architecture, each core may be able to keep executing µ-ops from one or more pipelines until the cache line is ready
      • two cores on different chips may not share a cache, but still need to co-ordinate access to the bus: ideally, whichever chip didn't issue the read will simply snoop the response
    • if they both want to write:

      • two cores on the same chip will just be writing to the same cache, and that only needs to be flushed to RAM once. In fact, since memory will be read from and written to RAM per cache line, writes at distinct but sufficiently close addresses can be coalesced into a single write to RAM

      • two cores on different chips do have a conflict, and the cache line will need to be written back to RAM by chip1, fetched into chip2's cache, modified and then written back again (no idea whether the write/fetch can be coalesced by snooping)

  2. If two cores tried to access different addresses ...

    For a single access, the CAS latency means two operations can potentially be interleaved to take no longer (or perhaps only a little longer) than if the bus were idle.

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So, can multiple CPU's / cores access the same RAM simutaneously, or is what I'm saying correct?

There are many different machine architectures out there, each with its own set of features. One category of multiprocessing machines is called MISD, for Multiple Instruction Single Data, and such machines are designed to provide the same data to several processors all at the same time. A related class of machines known as SIMD architectures (Single Instruction Multiple Data) are much more common and also provide access to the same memory at the same time, but the memory contains instructions instead of data. In both MIMD and SIMD, "access" means read access -- you can imagine the trouble you'd have if two units tried to write to the same location at the same time!

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