CPU is the abbreviation for central processing unit. Sometimes referred to simply as the central processor, but more commonly called processor

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Does the chipset also determines installablility of 32bit OS or 64bit OS? [migrated]

I have Fujitsu Lifebook A6025 with Pentium T2130 and Intel® 945GM/ ICH7-M chipset according to the spec. I want to upgrade the CPU to Intel Core 2 Duo Mobile T7400(Socket M) CPU. The T2130 CPU ...
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Are there CPUs that perform this possible L1 cache write optimization?

When the CPU with an L1 cache does a write, what normally happens is that (assuming that the cache line that it is writing to is already in the L1 cache) the cache (in addition to updating the data) ...
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Handling exceptions in multiple-issue CPUs

From what I read, VLIWs execute instructions in bundles, i.e. the CPU loads a bundle of instructions and dispatches them all at once. This is possible because the compiler scheduled instructions in ...
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What could “move an instruction without a 16-bit bus” mean?

Spoiler alert! This question (and, possibly, answers) could contain spoilers regarding "Halt and Catch Fire" TV series. Background I'm a web deleloper and do not have a CS degreee, so my ...
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Which language is a BIOS written in?

As I understand, the BIOS code/bitstream that is held in the ROM should be generic (work alongside with multiple CPU types or ISAs). In addition, I saw mentioned on the web that it is possible to dump ...
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Cost of cache coherency/sharing data across multiple cores?

If I have two CPU cores, one is writing a particular cache line and the other core wishes to Read Write the same cache line, what are the costs (in cycles) for doing so? I am a little unsure ...
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Why do we have to wait for I/O?

It's always been known that Disk operations are slow and we know the reasons why they are slow. So the question here is why do we have to wait for I/O or why is there such a thing as IOWait, etc.? I ...
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Pre-calculate values or not on Raspberry Pi

Say that you want to rotate something 360 steps 100 times. You now have a choise to pre-calculate 360 sin and cos values once and then use the stored values 100 times, or you can calculate sin and cos ...
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What is a latency-bound and a memory-bound application in HPC?

I understand that in HPC hybrid systems, for instance a MIC architecture, main memory access is much slower than access to data in own cache or in the cache of another core. I read that HPC MIC ...
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109 views

Relationship of common MCUs/CPUs to FPGA and ASIC

I'm trying to understand the relationship between "common" MCUs/CPUs such as Intel, AMD, PowerPC, AVR, ARM, etc. and FPGAs and ASICs. Here is my understanding: These commons MCUs/CPUs (again, ...
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Compiling and deploying a C program to an MCU running an RTOS

Please note: Even though I'm specifically talking about an RTOS called Embox here, and even though I'm talking about AVR/ARm, I think this question can be answered by anybody whose ever done a fair ...
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Compiling and deploying RTOS to an MCU

Please note: Even though I'm specifically talking about an RTOS called Embox here, and even though I'm talking about AVR/ARm, I think this question can be answered by anybody whose ever done a fair ...
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1answer
358 views

How does a program talk to a graphics card?

I have heard that GPU's are better at performing certain tasks than a CPU. My question is, how does a program tell a graphics card to process something instead of the CPU? Does the program talk to the ...
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1answer
125 views

Translation Lookaside buffer - Lookup By Page Size

I am having a hard time finding documentation that explains precisely how the various TLB caches are used in modern processors. Most modern processors have separate TLBs for code/data. That in itself ...
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93 views

What parallelism happens in a vector processor?

From Tanebaum's Structured Computer Organization A vector processor is very efficient at executing a sequence of operations on pairs of data elements. All of the operations are performed in a ...
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129 views

What does “issue or start an instruction” mean?

From Section 2.1.3 RISC vs CISC from Structured Computer Organization by Tanenbaum, While the initial emphasis was on simple instructions that could be executed quickly, it was soon realized ...
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213 views

Send heavy computation jobs from web server to another process and wait for response

I know it is a common practice to send cpu-bounded heavy tasks to background processes, in order to free a web server to serve other requests. But - what if the request must know the result of that ...
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Is a 1 < 10 comparison less expensive than 1 < 1000000?

I just used ~1 billion as the count for a z-index in CSS, and was thinking about the comparisons that must go on. Is there a difference in performance on the ALU level in comparisons between very ...
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12answers
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Why would a program require a specific minimum number of CPU cores?

Is it possible to write code (or complete software, rather than a piece of code) that won't work properly when run on a CPU that has less than N number of cores? Without checking it explicitly and ...
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1answer
589 views

Understanding memory update propagation in x86/x86-64 CPU L1/L2/L3 caches and RAM

I'm trying to understand in a general sense how L1/L2 (and now L3 caches) are updated and how the updates are propagated in a multi-core x86/x86-64 CPU to the other cores and eventually RAM. Assuming ...
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1answer
344 views

Developing a compiler for a self made CPU Architecture

Recently ive been consumed by creating my own simple CPU architecture that at some point could be easily implemented in hardware (No FPGA, but actual Logic Gate circuits). Naturally to fulfill this ...
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362 views

Hardware accelerated text processing

Graphics processing units (GPUs) are very common and allow for efficient, parallel processing of floating point numbers. PPUs (Physics Processing Units) used to be a buzzword several years ago but ...
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1answer
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Is the JVM “heap” inside the JVM software, or inside the physical computer?

I wanted to as this question about VMs in general, but focused it to JVM implementations only so this doesn't get closed as too broad. The JVM has a concept of a "heap". If my understanding is ...
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310 views

How does the CPU access the values of stack-allocated variables? [duplicate]

Consider the following C++ function: void doStuff() { Thing thingA; Thing thingB; thingA.doSomething(); // .. etc } During the execution of this function, variables thingA and ...
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Why should your code not use 100% CPU? [closed]

I'm speaking specifically about a C# .NET 4 program running on Windows XP or higher, but general answers are also acceptable. Assume an already optimized and efficient program. The problem here is ...
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Why do executables depend on the OS but not on the CPU?

If I write a C program and compile it to an .exe file, the .exe file contains raw machine instructions to the CPU. (I think). If so, how is it possible for me to run the compiled file on any computer ...
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Is there still any value in learning assembly languages today? [closed]

Specifically for a game programmer. If you really needed some assembly routines you could look for help, whereas back in the 80s/90s it was one of the mainstream languages. I read that compilers can ...
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Japanese Multiplication simulation - is a program actually capable of improving calculation speed?

I'd like to write a simulation of Japanese Multiplication to get benchmarks on large calculations utilizing the shortcut vs traditional CPU multiplication. I'm curious as to whether it makes sense to ...
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1answer
310 views

Do you have a metaphor for cache/data latencies? [closed]

From this answer about latencies, we have some numbers (yes, caveat caveat) for latencies when coding (slightly edited): L1 cache reference 0.5 ns Branch mispredict 5 ns L2 cache reference 7 ns Main ...
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1answer
304 views

Can we still consider that Moore's law still holds true regarding the consequence on CPU speed? [closed]

Moore's law is an empirical law and in simple terms states that the number of transistors on integrated circuits doubles approximately every two years. One of the consequences of Moore's law is that ...
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640 views

How Byte loading/storing is implemented By the CPU?

I know that in 32bit machine, cpu read from memory 32bits at a time. since the registers in this case is 32bit in size too, I can understand how this works. What I don't understand is how the cpu ...
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628 views

Multi-level paging tables

Referring to the image here: From http://en.wikipedia.org/wiki/File:X86_Paging_4K.svg Could somebody please explain something for me? I don't get exactly how this works. As I understand it the ...
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446 views

Intel Nehalem/SB/IB/Haswell CPUs, cache vs TLB

On the Nehalem+ architecture Intel CPUs what is the interaction between the L1 cache, L2 cache, L1 DTLB and L2 DTLB? On all the images I have found there isnt a clear explanation whether the CPU looks ...
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1answer
179 views

How does Branch Target Prediction differ from Branch Prediction?

I do not understand how BTP differs from BP? Yes I understand BP evaluates whether a conditional is true/false, but surely implicitly this also determines the "target" instruction? If I predict the ...
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1answer
844 views

How does the CPU know when it received RAM data and instructions?

Well, the title is pretty much self explanatory, but I'll expound it a bit, and say the origin of my question. So, I've been wondering as to how the CPU knows when it received the RAM. I'm pretty ...
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1answer
497 views

Working with CPU cycles in Gameboy Advance

I am working on an GBA emulator and stuck at implementing CPU cycles. I just know the basic knowledge about it, each instruction of ARM and THUMB mode as each different set of cycles for each ...
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How long is a typical modern microprocessor pipeline?

I learnt some about pipelining but those were 4-stage and 5-stage and I think that modern pipelining typical is much longer and more complicated in practice. How long are typical pipelines and how ...
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What are CPU registers?

This question has been bothering me for some time now and today I figured I would Google it. I've read some stuff about it and it seemed very similar to what I've always known as processor cache. Is ...
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1answer
537 views

Can we illustrate a CPU pipeline with a UML sequence diagram?

I study multicore pipelining and the diagrams are not UML sequence diagrams for instance Why not remake this diagram like an UML sequence diagram, would not that be more clear so that we can see ...
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Performance of single-assignment ADT oriented code on modern CPUs

Working in immutable data with single assignments has the obvious effect of requiring more memory, one would presume, because you're constantly creating new values (though compilers under the covers ...
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1answer
339 views

Is there genetic relationship between ARM and PDP-11 architectures?

Reading about ARM architecture I found many similarities to PDP-11 architecture which did not exist between ARM and x86. For example, General-purpose registers named Rx compared to AX, BX,... for ...
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Can multiple CPU's / cores access the same RAM simutaneously?

This is what I guess would happen: If two cores tried to access the same address in RAM, one would have to wait for the other to access the RAM. The second time that each core would try to access ...
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Instruction vs data cache usage

Say I've got a cache memory where instruction and data have different cache memories ("Harvard architecture"). Which cache, instruction or data, is used most often? I mean "most often" as in time, not ...
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Do compilers have to be written for each model of CPU?

Do you need to take account of the different processors and their instructions when writing a compiler? Have instructions been standardised? Or what tools and techniques are available to assist with ...
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Cloud computing platforms only have one CPU. Does this mean I shouldn't use Parallel Programming?

Almost every cloud instance I can find only offers one CPU. Why is this only one CPU now, and should I expect this to increase in the future? Does this design impact my code design so that I exclude ...
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4answers
2k views

What is the meaning of the sentence “we wanted it to be compiled so it’s not burning CPU doing the wrong stuff.”

I was reading this article. It has the following paragraph. And did Scala turn out to be fast? Well, what’s your definition of fast? About as fast as Java. It doesn’t have to be as fast as C or ...
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Benchmarking CPU processing power

Provided that many tools for computers benchmarking are available already, I'd like to write my own, starting with processing power measurement. I'd like to write it in C under Linux, but other ...
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How do I balance program CPU reverse compatibility whist still being able to use cutting edge features?

As I learn more about C and C++ I'm starting to wonder: How can a compiler use newer features of processors without limiting it just to people with, for example, Intel Core i7's? Think about it: new ...
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590 views

Computers that operate exclusively on boolean algebra

I was wondering if there are any computers that operate exclusively on boolean operations. For example, no add, sub, mult, or div in the instruction set (although these could be emulated with the ...
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Why does the stack grow downward?

I'm assuming there's a history to it, but why does the stack grow downward? It seems to me like buffer overflows would be a lot harder to exploit if the stack grew upward...