4
votes
2answers
391 views

How long is a typical modern microprocessor pipeline?

I learnt some about pipelining but those were 4-stage and 5-stage and I think that modern pipelining typical is much longer and more complicated in practice. How long are typical pipelines and how ...
2
votes
1answer
276 views

Can we illustrate a CPU pipeline with a UML sequence diagram?

I study multicore pipelining and the diagrams are not UML sequence diagrams for instance Why not remake this diagram like an UML sequence diagram, would not that be more clear so that we can see ...
24
votes
1answer
580 views

Performance of single-assignment ADT oriented code on modern CPUs

Working in immutable data with single assignments has the obvious effect of requiring more memory, one would presume, because you're constantly creating new values (though compilers under the covers ...
14
votes
2answers
5k views

Why are there separate L1 caches for data and instructions?

Just went over some slides and noticed that the L1 cache (at least on Intel CPUs) distinguishes between data and instruction cache, I would like to know why this is..