CPU is the abbreviation for central processing unit. Sometimes referred to simply as the central processor, but more commonly called processor

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7answers
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Is a 1 < 10 comparison less expensive than 1 < 1000000?

I just used ~1 billion as the count for a z-index in CSS, and was thinking about the comparisons that must go on. Is there a difference in performance on the ALU level in comparisons between very ...
57
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3answers
9k views

Which language is a BIOS written in?

As I understand, the BIOS code/bitstream that is held in the ROM should be generic (work alongside with multiple CPU types or ISAs). In addition, I saw mentioned on the web that it is possible to dump ...
55
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12answers
8k views

Why would a program require a specific minimum number of CPU cores?

Is it possible to write code (or complete software, rather than a piece of code) that won't work properly when run on a CPU that has less than N number of cores? Without checking it explicitly and ...
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10answers
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Why should your code not use 100% CPU? [closed]

I'm speaking specifically about a C# .NET 4 program running on Windows XP or higher, but general answers are also acceptable. Assume an already optimized and efficient program. The problem here is ...
30
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1answer
923 views

Performance of single-assignment ADT oriented code on modern CPUs

Working in immutable data with single assignments has the obvious effect of requiring more memory, one would presume, because you're constantly creating new values (though compilers under the covers ...
19
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3answers
7k views

Why does the stack grow downward?

I'm assuming there's a history to it, but why does the stack grow downward? It seems to me like buffer overflows would be a lot harder to exploit if the stack grew upward...
18
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6answers
6k views

Why do we have to wait for I/O?

It's always been known that Disk operations are slow and we know the reasons why they are slow. So the question here is why do we have to wait for I/O or why is there such a thing as IOWait, etc.? I ...
18
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3answers
21k views

What are CPU registers?

This question has been bothering me for some time now and today I figured I would Google it. I've read some stuff about it and it seemed very similar to what I've always known as processor cache. Is ...
17
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6answers
5k views

How often do CPUs make calculation errors?

In Dijkstra's Notes on Structured Programming he talks a lot about the provability of computer programs as abstract entities. As a corollary, he remarks how testing isn't enough. E.g., he points out ...
16
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2answers
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Why are there separate L1 caches for data and instructions?

Just went over some slides and noticed that the L1 cache (at least on Intel CPUs) distinguishes between data and instruction cache, I would like to know why this is..
15
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2answers
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OpenGL CPU vs. GPU [closed]

So I've always been under the impression that doing work on the GPU is always faster than on the CPU. Because of this, in OpenGL, I usually try to do intensive tasks in shaders so they get the speed ...
10
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4answers
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What is the meaning of the sentence “we wanted it to be compiled so it’s not burning CPU doing the wrong stuff.”

I was reading this article. It has the following paragraph. And did Scala turn out to be fast? Well, what’s your definition of fast? About as fast as Java. It doesn’t have to be as fast as C or ...
10
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7answers
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When should I be offloading work to a GPU instead of the CPU?

Newer systems such as OpenCL are being made so that we can run more and more code on our graphics processors, which makes sense, because we should be able to utilise as much of the power in our ...
8
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4answers
7k views

How do lines of code get executed by the CPU?

I'm trying to really understand how exactly a high-level language is converted into machine code and then executed by the cpu. I understand that the code is compiled into machine code, which is the ...
7
votes
2answers
5k views

Is this a valid smartphone CPU vs. desktop CPU speed comparison (Android G1 vs. old Pentium 4 desktop)?

I am trying to estimate speed differences when creating code on my desktop PC that will be ported to Android phones. I don't need to be exact, but a good estimation will help stop me from creating ...
7
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3answers
249 views

Are there CPUs that perform this possible L1 cache write optimization?

When the CPU with an L1 cache does a write, what normally happens is that (assuming that the cache line that it is writing to is already in the L1 cache) the cache (in addition to updating the data) ...
6
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2answers
3k views

How long is a typical modern microprocessor pipeline?

I learnt some about pipelining but those were 4-stage and 5-stage and I think that modern pipelining typical is much longer and more complicated in practice. How long are typical pipelines and how ...
6
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5answers
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Can multiple CPU's / cores access the same RAM simutaneously?

This is what I guess would happen: If two cores tried to access the same address in RAM, one would have to wait for the other to access the RAM. The second time that each core would try to access ...
6
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3answers
1k views

Cloud computing platforms only have one CPU. Does this mean I shouldn't use Parallel Programming?

Almost every cloud instance I can find only offers one CPU. Why is this only one CPU now, and should I expect this to increase in the future? Does this design impact my code design so that I exclude ...
6
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2answers
359 views

Programming language constructs for cache optimization?

Clearly optimizing cache usages is bound to improve my program efficiency. Surprisingly, I don't see too many programming languages actually having this sort of a feature. So here's my question: ...
5
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3answers
332 views

How do I balance program CPU reverse compatibility whist still being able to use cutting edge features?

As I learn more about C and C++ I'm starting to wonder: How can a compiler use newer features of processors without limiting it just to people with, for example, Intel Core i7's? Think about it: new ...
5
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3answers
1k views

What's so special about x64 and programming x86? [closed]

I know this is a little funny question, but I didn't have the chance to realize what makes any difference when programming x64 or x86 at high level languages (.NET for instance). Any explanations ...
4
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3answers
2k views

Japanese Multiplication simulation - is a program actually capable of improving calculation speed?

I'd like to write a simulation of Japanese Multiplication to get benchmarks on large calculations utilizing the shortcut vs traditional CPU multiplication. I'm curious as to whether it makes sense to ...
4
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3answers
2k views

Why do executables depend on the OS but not on the CPU?

If I write a C program and compile it to an .exe file, the .exe file contains raw machine instructions to the CPU. (I think). If so, how is it possible for me to run the compiled file on any computer ...
4
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3answers
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CPU Architecture and floating-point math

I'm trying to wrap my head around some details about how floating point math is performed on the CPU, trying to better understand what data types to use etc. I think I have a fairly good ...
4
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2answers
274 views

Benchmarking CPU processing power

Provided that many tools for computers benchmarking are available already, I'd like to write my own, starting with processing power measurement. I'd like to write it in C under Linux, but other ...
4
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1answer
534 views

Working with CPU cycles in Gameboy Advance

I am working on an GBA emulator and stuck at implementing CPU cycles. I just know the basic knowledge about it, each instruction of ARM and THUMB mode as each different set of cycles for each ...
3
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5answers
325 views

Based on what I read in “Inside the Machine”, is this approach to branches more optimal?

So I have been reading Inside the Machine by Jon Stokes. It is a FANTASTIC book, and it has got me thinking about the effects of programming on processors... Given a branch unit in a CPU and a ...
3
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2answers
1k views

Do compilers have to be written for each model of CPU?

Do you need to take account of the different processors and their instructions when writing a compiler? Have instructions been standardised? Or what tools and techniques are available to assist with ...
3
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1answer
718 views

Understanding memory update propagation in x86/x86-64 CPU L1/L2/L3 caches and RAM

I'm trying to understand in a general sense how L1/L2 (and now L3 caches) are updated and how the updates are propagated in a multi-core x86/x86-64 CPU to the other cores and eventually RAM. Assuming ...
2
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3answers
8k views

Is there still any value in learning assembly languages today? [closed]

Specifically for a game programmer. If you really needed some assembly routines you could look for help, whereas back in the 80s/90s it was one of the mainstream languages. I read that compilers can ...
2
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1answer
943 views

How does the CPU know when it received RAM data and instructions?

Well, the title is pretty much self explanatory, but I'll expound it a bit, and say the origin of my question. So, I've been wondering as to how the CPU knows when it received the RAM. I'm pretty ...
2
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1answer
377 views

Developing a compiler for a self made CPU Architecture

Recently ive been consumed by creating my own simple CPU architecture that at some point could be easily implemented in hardware (No FPGA, but actual Logic Gate circuits). Naturally to fulfill this ...
2
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2answers
264 views

Compiling and deploying a C program to an MCU running an RTOS

Please note: Even though I'm specifically talking about an RTOS called Embox here, and even though I'm talking about AVR/ARm, I think this question can be answered by anybody whose ever done a fair ...
2
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1answer
170 views

Is the JVM “heap” inside the JVM software, or inside the physical computer?

I wanted to as this question about VMs in general, but focused it to JVM implementations only so this doesn't get closed as too broad. The JVM has a concept of a "heap". If my understanding is ...
2
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1answer
350 views

Is there genetic relationship between ARM and PDP-11 architectures?

Reading about ARM architecture I found many similarities to PDP-11 architecture which did not exist between ARM and x86. For example, General-purpose registers named Rx compared to AX, BX,... for ...
2
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1answer
340 views

Do you have a metaphor for cache/data latencies? [closed]

From this answer about latencies, we have some numbers (yes, caveat caveat) for latencies when coding (slightly edited): L1 cache reference 0.5 ns Branch mispredict 5 ns L2 cache reference 7 ns Main ...
2
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3answers
623 views

Computers that operate exclusively on boolean algebra

I was wondering if there are any computers that operate exclusively on boolean operations. For example, no add, sub, mult, or div in the instruction set (although these could be emulated with the ...
2
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1answer
100 views

Compiling and deploying RTOS to an MCU

Please note: Even though I'm specifically talking about an RTOS called Embox here, and even though I'm talking about AVR/ARm, I think this question can be answered by anybody whose ever done a fair ...
2
votes
1answer
575 views

Can we illustrate a CPU pipeline with a UML sequence diagram?

I study multicore pipelining and the diagrams are not UML sequence diagrams for instance Why not remake this diagram like an UML sequence diagram, would not that be more clear so that we can see ...
2
votes
1answer
188 views

How does Branch Target Prediction differ from Branch Prediction?

I do not understand how BTP differs from BP? Yes I understand BP evaluates whether a conditional is true/false, but surely implicitly this also determines the "target" instruction? If I predict the ...
2
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0answers
71 views

Handling exceptions in multiple-issue CPUs

From what I read, VLIWs execute instructions in bundles, i.e. the CPU loads a bundle of instructions and dispatches them all at once. This is possible because the compiler scheduled instructions in ...
1
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2answers
104 views

What could “move an instruction without a 16-bit bus” mean?

Spoiler alert! This question (and, possibly, answers) could contain spoilers regarding "Halt and Catch Fire" TV series. Background I'm a web deleloper and do not have a CS degreee, so my ...
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3answers
143 views

Pre-calculate values or not on Raspberry Pi

Say that you want to rotate something 360 steps 100 times. You now have a choise to pre-calculate 360 sin and cos values once and then use the stored values 100 times, or you can calculate sin and cos ...
1
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1answer
497 views

How does a program talk to a graphics card?

I have heard that GPU's are better at performing certain tasks than a CPU. My question is, how does a program tell a graphics card to process something instead of the CPU? Does the program talk to the ...
1
vote
2answers
471 views

Hardware accelerated text processing

Graphics processing units (GPUs) are very common and allow for efficient, parallel processing of floating point numbers. PPUs (Physics Processing Units) used to be a buzzword several years ago but ...
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2answers
373 views

How does the CPU access the values of stack-allocated variables? [duplicate]

Consider the following C++ function: void doStuff() { Thing thingA; Thing thingB; thingA.doSomething(); // .. etc } During the execution of this function, variables thingA and ...
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2answers
147 views

What does “issue or start an instruction” mean?

From Section 2.1.3 RISC vs CISC from Structured Computer Organization by Tanenbaum, While the initial emphasis was on simple instructions that could be executed quickly, it was soon realized ...
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1answer
153 views

Relationship of common MCUs/CPUs to FPGA and ASIC

I'm trying to understand the relationship between "common" MCUs/CPUs such as Intel, AMD, PowerPC, AVR, ARM, etc. and FPGAs and ASICs. Here is my understanding: These commons MCUs/CPUs (again, ...
1
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1answer
318 views

Can we still consider that Moore's law still holds true regarding the consequence on CPU speed? [closed]

Moore's law is an empirical law and in simple terms states that the number of transistors on integrated circuits doubles approximately every two years. One of the consequences of Moore's law is that ...