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Intel Nehalem/SB/IB/Haswell CPUs, cache vs TLB

On the Nehalem+ architecture Intel CPUs what is the interaction between the L1 cache, L2 cache, L1 DTLB and L2 DTLB? On all the images I have found there isnt a clear explanation whether the CPU looks ...
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146 views

What did machine code for 4-bit architecture look like?

I don't know how a 4-bit instruction could be enough to do something so I read about the Intel 4004 and it says that it used 8-bit instructions and then I can understand how opcode and numbers has ...
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1answer
187 views

Transactional Memory vs Mutex and Locks

Just found out that Intel processors now have Transactional Memory support !!!! I learned about Transactional operations in my dB/OS class, it is a very simple concept: entire operation is executed or ...
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1answer
208 views

Cross Compile Arm Program to Intel

I have searched around for a way to run a program meant for ARM processors on an Intel computer, but I can only find ways to do the reverse, to compile Intel programs for ARM. Are there any ...
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1answer
342 views

Intel mnemonic to machine code converter library

I'm trying to do the following: take a single IA32 instruction in the Intel syntax (such as ADD EAX, EBX) and produce the corresponding machine code for this instruction. Is there some small library, ...
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1answer
137 views

MASS equivalent for intel compilers and architectures

I was looking for an Intel alternative to MASS IBM libraries (Mathematical Acceleration Subsystem). I know Intel implements MKL libraries, but I d'nt know if there is a specific Math acceleration ...
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Do you consider mainframe as part of large application deployments?

When you are setting up your system landscape for large and/or multiple application deployments, do you consider mainframe? If not, why not? If so, what factors are you considering. If you take a ...