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Your tests are basically looping straight thru memory, so the cache is working for you roughly as follows: You touch some memory not in any cache, which triggers a cache line load from the closest cache, L1, which cascades thru the L2 and L3 caches, until main memory is reached. An L3-cache-line-sized chunk of data from main memory is fetched to fill the ...


Once upon a time (80386 era) most computers had less than 16 MiB of RAM, there were no memory mapped PCI devices, and 1 GiB of space sounded insanely huge (especially for a "temporary kernel" that was only expected to be used until GNU finished their own kernel). Mapping all of the physical RAM into kernel space sounded like a good idea; so that's what ...

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